
Vhdl
Zainalabedin Navabi
₹7,516

RT Level Synthesis, Testbench and Verification
McGraw-Hill · 2005 · Hardcover
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Verilog Digital System Design: RT Level Synthesis, Testbench and Verification is written by Zainalabedin Navabi.
Its main subjects are Electronic digital computers, Computer-aided design, Verilog (Computer hardware description language) and Circuits & components.