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Verification by Error Modeling

Using Testing Techniques in Hardware Verification: 25

by Zeljko Zilic, Katarzyna Radecka

Springer-Verlag New York Inc. · 2003 · Hardcover

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About this book

Verification by Error Modeling: Using Testing Techniques in Hardware Verification: 25 by Zeljko Zilic & Katarzyna Radecka is a 216-page hardcover edition published by Springer-Verlag New York Inc. in 2003.

Topics covered include Computer-aided design, Error analysis (Mathematics), Integrated circuits and Verification.

Book details

ISBN-13
9781402076527
ISBN-10
1402076525
Authors
Zeljko Zilic, Katarzyna Radecka
Published
2003
Edition
2003 ed.
Binding
Hardcover
Pages
216
Language
English
Condition
New

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