
Thermal-Aware Testing of Digital VLSI Circuits and Systems
Santanu Chattopadhyay
₹4,311

Using Testing Techniques in Hardware Verification: 25
by Zeljko Zilic, Katarzyna Radecka
Springer-Verlag New York Inc. · 2003 · Hardcover
Free delivery. Nothing extra to pay at checkout.
Verification by Error Modeling: Using Testing Techniques in Hardware Verification: 25 by Zeljko Zilic & Katarzyna Radecka is a 216-page hardcover edition published by Springer-Verlag New York Inc. in 2003.
Topics covered include Computer-aided design, Error analysis (Mathematics), Integrated circuits and Verification.