Formal Semantics and Proof Techniques for Optimizing VHDL Models

Name: Formal Semantics and Proof Techniques for Optimizing VHDL Models
Brand: Springer
SKU: 9781461373315
Price: 7762.00 INR
Availability: InStock

by Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey

Springer · 2012

₹7,762

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About this book

Formal Semantics and Proof Techniques for Optimizing VHDL Models by Kothanda Umamageswaran, Sheetanshu L. Pandey & others is a 158-page book published by Springer in 2012.

Its main subjects are Computer hardware, Systems engineering, Engineering and Computer-aided design.