
Irrationality
Stuart Sutherland
₹3,080

Using Systemverilog for Asic and Fpga Design
Createspace Independent Pub · 2017
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Published by Createspace Independent Pub in 2017, Rtl Modeling with Systemverilog for Simulation and Synthesis: Using Systemverilog for Asic and Fpga Design by Stuart Sutherland runs to 488 pages.
Topics covered include Verilog (Computer hardware description language) and Computer simulation.