
ASIC and FPGA Verification
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Methods and Tools for Verification of System-Level Designs
by Sorin Lerner, Sudipta Kundu, Rajesh K. Gapta
Springer Verlag · 2011
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High-Level Verification: Methods and Tools for Verification of System-Level Designs by Sorin Lerner, Sudipta Kundu & others is a 167-page book published by Springer Verlag in 2011.
The book deals with Systems engineering, Engineering, Computer-aided design and Testing.